The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device which receives an external clock to generate an internal clock.
In general, semiconductor memory devices including double data rate synchronous dynamic random access memory (DDR SDRAM) receive external clock signals to generate internal clock signals. These generated internal clock signals are inputted into various circuits in a semiconductor memory device and used to operate such circuits. In order to compensate for a clock skew of an external clock signal and an internal clock signal, a semiconductor memory device is provided therein with a clock synchronous circuit. Representative examples of clock synchronous circuits include phase locked loop (PLL) circuits and delay locked loop (DLL) circuits.
In recent years, as the operation frequency of semiconductor memory devices is increased up to a high frequency band more than GHz, a PLL circuit, which is easy to generate multi-clock signals and has a frequency multiplication function, is widely used as a clock synchronizing circuit.
FIG. 1 is a block diagram illustrating a conventional clock synchronizing circuit.
Referring to FIG. 1, the clock synchronizing circuit includes a buffering unit 110, a PLL 130, and a phase mixing unit 150.
The buffering unit 110 buffers an external clock signal CLK_EXT to generate a reference clock signal CLK_REF.
The PLL 130 receives the reference clock signal CLK_REF to generate a plurality of clock signals CLK_PLL0, CLK_PLL90, CLK_PLL180 and CLK_PLL270. The plurality of clock signals CLK_PLL0, CLK_PLL90, CLK_PLL180 and CLK_PLL270 are signals having a constant phase difference from each other. In more detail, the plurality of clock signals CLK_PLL0, CLK_PLL90, CLK_PLL180 and CLK_PLL270 include a first clock signal CLK_PLL0, a second clock signal CLK_PLL90 having a phase difference of 90° from the first clock signal CLK_PLL0, a third clock signal CLK_PLL180 having a phase difference of 180° from the first clock signal CLK_PLL0, and a fourth clock signal CLK_PLL270 having a phase difference of 270° from the first clock signal CLK_PLL0.
The phase mixing unit 150 receives and mixes the first to fourth clock signals CLK_PLL0, CLK_PLL90, CLK_PLL180 and CLK_PLL270 to generate a desired internal clock CLK_INT. The generated internal clock CLK_INT passes through an actual clock/data path and is used to output data. As a result, data can be synchronized with the external clock CLK_EXT.
The concrete circuit constructions of the buffering unit 110, the PLL 130 and the phase mixing unit 150 are well known to those skilled in the art, and accordingly their detailed descriptions will be omitted.
As aforementioned, the phase mixing unit 150 mixes the plurality of clock signals CLK_PLL0, CLK_PLL90, CLK_PLL180 and CLK_PLL270 to generate the internal clock CLK_INT. The phase mixing unit 150 often uses a DLL. When the phase mixing unit 150 uses a DLL, the internal clock CLK_INT is generated by using any selected from the plurality of clock signals CLK_PLL0, CLK_PLL90, CLK_PLL180 and CLK_PLL270.
With products produced recently being gradually miniaturized, there is a need to improve a circuit occupying a relatively large area, such as the phase mixing unit 150. In the case that the phase mixing unit 150 uses the DLL, there is a need for improvement of a large area. In particular, since the DLL generates an additional delay time due to a locking operation, there is also needed an improvement for a faster operation of the circuit.